1. Field of the Invention
The present invention relates to a surface discharge AC plasma display panel, a method of driving same and a plasma display apparatus employing same.
2. Description of the Related Art
The plasma display panel (PDP) has good visibility because it generates its own light, is thin and can be made with large-screen and high-speed display. For these reasons it is attracting interest as a replacement for the CRT display. Especially, a surface discharge AC PDP is suitable for full color display. Therefor, there are high expectations in the field of high-vision and the demand for a higher quality image is increasing. A higher quality image is achieved by generating higher definition, a higher number of gradations, better brightness, lower brightness for black areas, higher contrast and the like. High definition is achieved by narrowing the pixel pitch, a higher number of gradations is achieved by increasing the number of subfields within a frame, higher brightness is achieved by increasing the number of times sustaining discharge is performed and lower brightness for deeper blacks is achieved by reducing the quantity of light emission during the reset period.
FIG. 30 shows the schematic structure of an surface discharge AC plasma display panel (PDP) 10P in the prior art.
On observer-side one of the glass substrates that face each other, electrodes X1 to X5 are formed parallel to one another at equal pitch and electrodes Y1 to Y5 are formed parallel to one another to form parallel pairs with the corresponding electrodes X1 to X5. On the other glass substrate, address electrodes A1 to A6 are formed in the direction that runs at a right angle to the aforementioned electrodes, and phosphor covers on that. Between the glass substrates that face each other, partitioning walls 171 to 177 and partitioning walls 191 to 196 are arranged intersecting each other in a lattice, to ensure that no erroneous display is made through discharge of one pixel affecting adjacent pixels.
The surface discharge PDPs have an advantage in that the phosphor do not become degraded due to the impact of ions on it since discharge occurs between adjacent electrodes on the same surface. However, since a pair of electrodes is provided for each of the display lines L1 to L5, the degree to which the pixel pitch can be reduced is limited and this is a stumbling block for achieving high definition. In addition, the scale of the drive circuit must be large since there is a high number of electrodes.
To deal with this problem, a PDP 10Q as shown in FIG. 31 has been disclosed in Japanese Patent Publication No. 5-2993 and No. 2-220330.
In the PDP 10Q, partitioning walls 191 to 199 are provided on the central lines of the electrodes X1 to X5 and Y1 to Y4, which are surface discharge electrodes, and these electrodes, except for the electrodes X1 and X5 at the two sides, i.e., the electrodes X2 to X4 and the electrodes Y1 to Y4, are commonly used by display lines that are adjacent in the direction of the address electrodes. With this, the number of electrodes is almost halved and the pixel pitch can be reduced, achieving higher definition compared to the PDP shown in FIG. 30. In addition, the scale of the drive circuit can also be halved.
However, in the publications cited above, since write is performed in linear sequence for the display lines L1 to L8, the discharge would affect adjacent pixels in the direction of the address electrodes if the partitioning walls 191 to 199 are omitted, resulting in erroneous display. Thus, the partitioning walls 191 to 199 cannot be omitted and this presents an obstacle to achieving higher definition by reducing the pixel pitch. In addition, it is not easy to provide the partitioning walls 191 to 199 on the central lines of the electrodes and, as a result, the PDP 10Q will be expensive to produce. Furthermore, in the publications mentioned above, a specific waveform of the voltage to be applied to the electrodes is not disclosed and, as a result, the invention has not been put into practical use. In order to make it possible to remove the partitioning walls running in the direction of the surface discharge electrodes, the distance between the electrodes at the two sides of each of the partitioning walls 191 to 196 must be increased in the structure shown in FIG. 30, so as to reduce the effect of their electric fields between that electrodes. Consequently, the pixel pitch increases, preventing achievement of higher definition. For instance, the distance between the electrodes Y1 and X2 (non display line) is 300 μm when the distance between the electrodes Y1 and X2 (display line) is 50 μm.
In addition, during the reset period, light is emitted because of the whole-screen (all pixel) discharge and brightness in the black display areas is increased, reducing the quality of the display.
Moreover, since the color of the phosphor is white or bright gray, incident light from the outside is reflected on the phosphor at non display line when observing an image on the PDP in bright place, lowering the contrast of the image.
In addition, since only one line can be addressed at a time, the address time cannot be reduced, and it is not possible to achieve a higher number of gradations by increasing the number of subfields or to achieve higher brightness by increasing the number of times sustaining discharge is performed.